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Title:
LATERAL JUNCTION TYPE FIELD-EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPS584978
Kind Code:
A
Abstract:

PURPOSE: To decrease gate leakage by shortening a distance α between a source and an upper gate to a distance necessary for obtaining breakdown voltage (BVSGO) between the source and the gate required and sufficiently widening a distance β between a drain and the upper gate.

CONSTITUTION: In the J-FET, the distance β between the drain 8 and the upper gate 4 is set to value longer than the distance α between the source 5 and the gate 4. Accordingly, the interchangeability of the source and the drain is lost and the BVSGO is increased to obtain only value required, but a depletion layer is widely extended to the drain side because the distance β is, on the other hand, selected at sufficiently large value. When a surface protective film is reinforced or a field plate electrode is attached onto the exposed end of a P-N junction 11 between an epitaxial layer 2 and the upper gate layer 4 through an insulating film, the depletion layer in the vicinity of the surface further increases the effect of its extension. When the depletion layer is widened, field focussing is weakened, excessive gate leakage currents are decreased and high-dielectric resistance operation is enabled.


Inventors:
MITARAI GOROU
Application Number:
JP10406581A
Publication Date:
January 12, 1983
Filing Date:
July 01, 1981
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L29/80; H01L21/337; H01L29/808; (IPC1-7): H01L29/80
Domestic Patent References:
JPS548476A1979-01-22
JPS5367371A1978-06-15
JPS554912A1980-01-14
Attorney, Agent or Firm:
Masuo Oiwa