PURPOSE: To utilize to the maximum an operating speed of a microprocessor and a memory, and to raise a performance of a device by extending a clock supplied to the microprocessor, only when a memory error is confirmed.

CONSTITUTION: A bus cycle BC2 shows a timing in case when a memory error is generated. When a memory error signal MEMERR is generated, an FF143 latches (in the case, a clear input of the FF is P4 and inactive) this signal by a timing of a time t15, and closes an AND gate 144 and 145. As a result, an input of an FF142 is controlled so that a bus cycle T4 does not fall at the next time t16, and the bus cycle T4 falls at the next time t17, by which the bus cycle is ended by one clock, and a data in which a memory error data has also been corrected is supplied to a microprocessor.