Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
BUS SUPERVISING CIRCUIT
Document Type and Number:
Japanese Patent JPS6080338
Kind Code:
A
Abstract:

PURPOSE: To attain ease of correspondence to change of order of transmission by using a signal and a transmission order number of the signal as an address and using a read-only memory storing a signal representing an error of the transmission order of the signal to supervise the transmission order.

CONSTITUTION: Operating permission signals S21∼S23 transmitted to a common bus are fed to an FF group via a gate G, an address strobe signal S3 and a data strobe signal S4 are transmitted directly to the FF group. The FF group stores the operating permission signal S2, the address strobe signal S3, the data strobe signal S4 and a transmission order number C read from an ROM and gives an input to the ROM by using them as an address. When the combination of them is in error, since an error signal (e) is stored in the said address, the state is written in an RAM and the content is recognized by reading the storage content (f) later.


Inventors:
FUKUSHIMA TOMOYOSHI
Application Number:
JP18827083A
Publication Date:
May 08, 1985
Filing Date:
October 07, 1983
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
G06F13/00; H04L12/00; (IPC1-7): G06F13/00
Attorney, Agent or Firm:
Sadaichi Igita