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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5923558
Kind Code:
A
Abstract:

PURPOSE: To prevent the influence of variations in a power source to be affected to other block such as a logic unit by individually connecting a circuit block and a power pad on the same semiconductor chip, supplying power from individual power sources, and isolating the wells formed in every block.

CONSTITUTION: Aluminum wirings La, Lb, Lc,... are connected from a power pad 1 to circuit blocks 2a, 2b, 2c,... and power voltage is applied to the wells 3a, 3b, 3c,.... The wirings La, Lb, Lc are respectively connected to the common lines 1a, 1b, 1c of the source electrodes of an FET in each block. Thus, when the voltage of the power source varies in the well 3b due to the operation of the logic unit 2b, the variation in the power source is transmitted to other blocks from Lb via the pad 1 and the other La, Lb, the influence is hardly affected, thereby improving the reliability of the circuit.


Inventors:
HONGOU TOYOHIKO
Application Number:
JP13195182A
Publication Date:
February 07, 1984
Filing Date:
July 30, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/822; H01L23/52; H01L27/04; H01L27/06; (IPC1-7): H01L27/04; H01L27/10
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)