PURPOSE: To obtain a universal device capable of varying the bit pattern of a read-only memory (ROM) by providing a sequence control processor which operates at byte-by-byte data transfer timing.

CONSTITUTION: The sequence control processor consists of a sequence counter 20, ROM21, and sequence register 22. This counter 20 counts the timing signal of data transfer on the side of a disk storage device successively and its counted value is used as an address of the memory 21. Bit pattern contents read out of the memory 21 are stored in the register 22. When the bit pattern has the 1st logical value, data is transferred from a specific data storage register to another register and when the bit pattern has the 2nd logical value, comparative arithmetic is performed. Further, when the pattern has the 3rd logical value, write or read data of an RAM is stored in the data storage register and when the bit pattern has the 4th logical value, the contents of the address register for the RAM are advanced.