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Title:
REVERSIBLE COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JPS60103729
Kind Code:
A
Abstract:

PURPOSE: To continue cyclicly and reflectedly binary N-digit forward and reverse counting by connecting an output of the most significant (N+1)-digit of a counter circuit as other input to each gate so as to extract an output of each gate.

CONSTITUTION: When a clock signal comes to a terminal CK, a counter circuit CRT starts forward count and since a level of a terminal Q(N+1) is logical 0, an output appearing output terminals O1, O2...ON of each exclusive OR gate is equal to an output of output terminals Q1, Q2...QN of the circuit CRT so as to obtain the forward count. When the forward count of the circuit CRT is advanced, the order of the incoming pulse is 2×(N-th power of 2)-1 and when the output of the terminals Q1, Q2.QN up to the binary N-digit is all logical 1 again, the output appearing the output terminals O1, O2...ON of the OR gate is all logical 0 and the reverse count is finished and the count is circulated.


Inventors:
UCHIDA YUKIO
Application Number:
JP21120283A
Publication Date:
June 08, 1985
Filing Date:
November 10, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04Q1/45; H03K23/00; H04M19/02; (IPC1-7): H03K23/00; H04M19/02; H04Q1/45
Domestic Patent References:
JPS51122366A1976-10-26
JPS51105259A1976-09-17
JPS57142698A1982-09-03
Attorney, Agent or Firm:
Sadaichi Igita



 
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