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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH04111293
Kind Code:
A
Abstract:

PURPOSE: To simplify a bus circuit and to reduce a chip size by using the circuit output of the OR of a power-on one-shot signal and a data transfer gate open/ close signal as the open/close signal of a switch.

CONSTITUTION: A column address decoder group 1, serial data selector group 2, data transfer gate open/close signal generation circuit 3, power-on one-shot signal generation circuit 4, data bus group 5 for column address decoder output transfer are provided, and a signal 1 is a data transfer gate open/close signal and is turned to a high level only when transferring a column address decoder output to a serial data selector. A signal 2 is a power-on one-shot signal and is turned to a high level temporarily when a power source is turned on. Thus, since the transfer gate is operated by the power-on one-shot signal as well, the data bus directly inputting the power-on one-shot signal to the serial data selector is not required and the increase of the chip size can be suppressed.


Inventors:
SAHO KAZUHISA
Application Number:
JP22928290A
Publication Date:
April 13, 1992
Filing Date:
August 30, 1990
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G11C11/401; (IPC1-7): G11C11/401
Domestic Patent References:
JPS6473599A1989-03-17
JPS63261598A1988-10-28
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)