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Title:
MANUFACTURE OF MOS SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5843561
Kind Code:
A
Abstract:

PURPOSE: To obtain an MOS semiconductor device which realizes excellent performance of operation and high integration density by preventing short-circuitting of the channel in such a conductive type of impurity provided in the step of activating heat treatment and having a large diffusion coefficient and by making almost equal the channel length of MOS transistor of different conductivity type to the design length.

CONSTITUTION: An SiO2 102 is formed at the side end of the gate electrode 62 on the area 32 to where the p channel MOS transistor diffusing the boron having a large diffusion coefficient is to be formed and the boron ion is implanted with the remaining SiO2 102 and gate electrode 62 used as the mask. Accordingly, the length between boron ion implanted layers 111 and 112 formed increases as much as the width of remaining SiO2 102. As a result, the short-circuitting of p channel can be prevented even when the boron having a large diffusion coefficient is diffused laterally in the succeeding thermal processing for activation. Therefore, a high speed operation of device can be realized without causing deterioration of threshold voltage and drain breakdown voltage.


Inventors:
TANAKA TAKESHI
Application Number:
JP14210981A
Publication Date:
March 14, 1983
Filing Date:
September 09, 1981
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L27/08; H01L21/8238; H01L29/78; (IPC1-7): H01L27/08; H01L29/78
Attorney, Agent or Firm:
Takehiko Suzue



 
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