PURPOSE: To accurately evaluate a logic circuit at high speed by issuing the output of an n-bit/m-stage memory operated by clock common to that of the logic circuit so as to change over both of them.

CONSTITUTION: The output of a logic circuit 1a is issued from an output terminal group 7a as the output of a semiconductor integrated circuit 8a through output buffers 4a-1-4a-n in a usual state. In a testing state, the output of the logic circuit 1a is stored in an n-bit/m-stage shift register 2a at the same speed as the input clock of the logic circuit 1a and, next, the speed of the clock is changed to make it possible to issue the output of the shift register 2a from the output terminal group 7a of the semiconductor integrated circuit 8a through the output buffers 4a-1-4a-n.