METHOD AND APPARATUS FOR TESTING AND MAINTAINING DATA PROCESSING SYSTEM

Japanese Patent JPS60151755

A

A test and maintenance system for use with a data processing system comprising a specialized circuit set wherein the circuit set registers can be configured into a serial array, a clock signal distribution system capable of delivering controlled clock signals to selected serial arrays, a maintenance data processor for providing predetermined signal groups, and addressing apparatus responsive to the predetermined signal groups for loading and unloading register arrays in response to the pre-determined signals. The disclosed apparatus permits a predetermined signal group to be entered into the serial register array, in a predetermined number of clock cycles (i.e. series of operations performed on the data), shifting of the resulting signals from the serial register array and signals outputting to data processing unit for display or analysis. By comparing the expected result for a given initial state with the actual result of an operation sequence, the accuracy of the operation of a data processing system, or any portion thereof, can be established. The test and maintenance system includes a group of registers and register cells through which data signals can be serially shifted. The serially coupled registers and register cells are coupled to active registers of the data processing systems and data signals can be extracted from or entered into the data processing system while the system is in operation. In this manner, the status of the system can be determined or control signals can be entered into the data processing system without halting operation.

JIEEMUZU ERU KINGU

JP20032584A

August 09, 1985

September 25, 1984

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HONEYWELL INF SYSTEMS

G01R31/3185; G06F11/267; G06F11/22; (IPC1-7): G06F11/22

Kyozo Yuasa

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