MULTIPROCESSOR COMPUTER SYSTEM AND COMPUTER MODULE

Japanese Patent JPS6148061

A

A multiprocessor computer system is described which consists of n computer modules. Each computer module includes a processor module and a reducing encoder for forming a data word from a code symbol. The code symbols are broadcast to all computer modules for further processing, so that a correct data word comprising K symbols can be reconstructed by means of a symbol-correcting code, while at the most t code symbols may be disturbed. For the connection of an external apparatus, the latter transmits A original versions to a corresponding number of computer modules. The original versions are broadcast to the computer modules as secondary, tertiary, ... versions during successive broadcast steps. Subsequently, decision steps are taken in the opposite sense, that is to say during a last step but one in majority decision is taken each time on the basis of a secondary version and the tertiary versions originating from the same original version as the relevant secondary version. When the broadcast has gone further than tertiary versions, majority decisions are taken during a last step but two on the basis of the quaternary and tertiary versions and the relevant majority decision results appear instead of the tertiary versions in the last step but one. During a final decision step, the original version is compared in a relevant computer module with any majority decision result which has been formed in the same computer module and which concerns a different original version.

TEIEISU KURORU
UIRIBURORUDOUSU YOHANESU BUAN

JP17438685A

March 08, 1986

August 09, 1985

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PHILIPS NV

G06F11/16; G06F11/18; G06F15/16; G06F15/177; (IPC1-7): G06F11/16; G06F15/16

Akihide Sugimura

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