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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5927566
Kind Code:
A
Abstract:

PURPOSE: To enable to cross a conductor wiring layer to a diffused wiring layer without decreasing the integrating density and increasing the number of steps by constructing the conductor wiring layer in a short width part formed on an insulating film corresponding to a gate insulating film to be connected by lateral diffusion at the forming time or to enable a punch through.

CONSTITUTION: The lateral widths l of short lateral width parts 20a, 24a are set in size that, by using a selective impurity diffusing method with a gate insulating film 24, a conductor wiring layer 20 and a field insulating film 12 as masks a diffused wiring layer 3 formed on the parts at both lateral sides of the film 24 of the main surface of a P type Si substrate 11 in a lateral groove 13 is connected by lateral diffusion in the part of the part 24a of the film 24 or electrically performed in a punch through manner. Even if the layer 20 and the layer 3 are formed by self-aligning method, the layers 3 formed at both lateral sides of the film 24 is connected by lateral diffusion at the part of the part 24a of the film 24 or electrically performed in a punch through manner.


Inventors:
MURAYAMA KEIICHI
Application Number:
JP13770882A
Publication Date:
February 14, 1984
Filing Date:
August 06, 1982
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G11C17/00; G11C17/18; H01L21/8246; H01L23/535; H01L27/112; H01L29/78; (IPC1-7): G11C17/00; H01L27/10; H01L29/78
Attorney, Agent or Firm:
Shinichi Kusano



 
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