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Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS60176265
Kind Code:
A
Abstract:

PURPOSE: To obtain large capacitance by a fine plane area by a method wherein a small hole is formed to the main surface of a semiconductor substrate, a buried cavity having width wider than the small hole is connected and shaped to the lower section of the small hole, an insulating film is formed on the whole surfaces of the small hole and the cavity and an insulated gate type capacitance with an electrode is shaped on the insulating film.

CONSTITUTION: An SiO2 film 13 is formed on a P type Si substrate 10 and bored selectively through directional dry etching, and a small hole is shaped through directional dry etching up to approximately 5μm depth of silicon in the substrate by using the opening. P ions are implanted to form an N+ type phosphorus ion implanting region 14, and an N+ type diffusion region 14' is shaped through heat treatment. Si in the substrate is etched under conditions, in which side etching is generated only in a high-concentration impurity region through directional dry etching, to shape a buried cavity section to the lower section of the small hole. The SiO2 film 13 is removed, an SiO2 film 11 is shaped on the surfaces of the small hole, the cavity and the substrate, and a polysilicon electrode 12 is formed on the surface of the film 11.


Inventors:
NAKAMAE MASAHIKO
Application Number:
JP3170384A
Publication Date:
September 10, 1985
Filing Date:
February 22, 1984
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L27/10; H01L21/8242; H01L27/108; (IPC1-7): H01L27/04; H01L27/10
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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