Title:
PROCESSOR RESET SYSTEM
Document Type and Number:
Japanese Patent JPS603778
Kind Code:
A
Abstract:
PURPOSE:To reset an abnormal processor without the influence upon the other processors when the processor becomes abnormal, by providing a communication right control part, a timer, a processor operation state monitor means, etc. CONSTITUTION:When a subprocessor 2 performs communication, it outputs a communication right request signal to a communication right control circuit 6. The circuit 6 gives the communication right to the processor 2, and then, a timer circuit 7 is started. In this case, if an abnormality occurs in the processor 2, the circuit 6 cancels the permission of the communication right given to the processor 2 through the circuit 7. A main processor 1 outputs an operation state reporting command to processors 2, 3, etc. successively from its operation monitor part 1-0, and processors 2, 3, etc. report operation states. However, the processor where an abnormality occurs does not report the operation state, and the processor 1 outputs a reset signal to this processor to reset it. The circuit 1-0, the circuit 7, etc. are provided to reset the processor, where an abnormality occurs, without exerting the influence upon the other processors when an abnormality occurs in the processor.
Inventors:
MORIYAMA YUTAKA
ANDOU YUKIHIRO
OOE SHIGERU
ANDOU YUKIHIRO
OOE SHIGERU
Application Number:
JP11141683A
Publication Date:
January 10, 1985
Filing Date:
June 21, 1983
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F15/16; G06F13/364; G06F15/177; (IPC1-7): G06F15/16
Domestic Patent References:
| JPS51147146A | 1976-12-17 | |||
| JPS5755461A | 1982-04-02 | |||
| JPS57143669A | 1982-09-04 |
Attorney, Agent or Firm:
Akira Yamatani
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