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Title:
MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5986258
Kind Code:
A
Abstract:

PURPOSE: To prevent the occurrence of improper C-E withstand voltage leakage by implanting ions by twice with a field oxidized film as a mask at the time of forming a base.

CONSTITUTION: An N type impurity layer (collector unit) 2 is formed on a P type silicon substrate 1, and silicon oxidized films 3a, 3b, a P type high density impurity layer (insulating layer) 4 and a silicon nitrided film 5 are formed. Then, once and twice P type ion implantations are carried out to form 2-stage density profile P type impurity layers (base) 8. Then, a hole B is formed by selectively etching, and an N type impurity is diffused to form an emitter unit 7. The base 8 becomes substantially uniform in thickness, a boron region in the boundary from a field insulating film is expanded, the base width has a margin, and an improper C-E withstand voltage leakage in the boundary can be reduced.


Inventors:
OOHIRA MASAAKI
Application Number:
JP19622782A
Publication Date:
May 18, 1984
Filing Date:
November 09, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L29/73; H01L21/331; H01L29/72; (IPC1-7): H01L29/72
Attorney, Agent or Firm:
Uchihara Shin