PURPOSE: To adjust a delay time easily and minutely for adjustment of a skew without increasing a layout area by adjusting an electric resistance which has an effect on an ability of an output section of a library cell to supply current for adjustment of the ability of the output section to supply current in a gate- array integrated circuit.

CONSTITUTION: A two-input NAND gate is constituted of two P-channel MOS transistors TP1 and TP2 and two N-channel MOS transistors TN1 and TN2. As shown by a layout, there are 20 contacts in all, 'x'-marked squares in the figure, which determine a resistance value having an effect on an output current value when an output current flows in an output section Y. The number of contacts which have an effect on an ability of the output section to supply current can be reduced from the maximum 20 to the minimum five, which is the minimum requirements for the NAND gate. When the number of contacts is reduced, a parasitic resistance value between a source and a drain of the MOS transistor increases and an ability of the output section Y to supply current decreases and thus a skew can be adjusted by making adjustments to a delay time of the NAND gate.