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Patent Searching and Data


Title:
AUTOMATIC CLEARING CIRCUIT
Document Type and Number:
Japanese Patent JPS5977532
Kind Code:
A
Abstract:

PURPOSE: To always generate an auto clear signal even if a power supply voltage is low and a fall time is slow by providing in parallel a series circuit of the second MOSFET and a capacitor on the series circuit of the first MOSFET and the capacitor.

CONSTITUTION: The first series circuit consisting of a P channel type MOSFET Q4 and a capacitor C5 is connected between a ground point and the power supply voltage VDD, and also a series circuit consisting of a capacitor C6 and an N channel type MOSFETQ5 is connected in parallel with the first series circuit. Subsequently, an FETQ4 is conducted and controlled by the power supply voltage VDD, also the FETQ5 is conducted and controlled by the potential of a connecting point N2 of the FETQ4 and the capacitor C5, and the potential of a connecting point N3 of the FETQ5 and the capacitor C6 is obtained as an auto clear signal ACL through an inverting circuit NOT. In this way, the signal ACL can be generated at all times irrespective of a fall time of the power supply voltage.


Inventors:
KAWASAKI MASAYUKI
Application Number:
JP18784182A
Publication Date:
May 04, 1984
Filing Date:
October 26, 1982
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H03K17/22; G06F1/24; (IPC1-7): G06F1/00
Attorney, Agent or Firm:
Takehiko Suzue