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Title:
GAAS GATE ARRAY INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS60152039
Kind Code:
A
Abstract:
PURPOSE:To enable to stably operate all fundamental cells even though the cells are respectively composed of the constitution of a direct-coupled FET logic, wherein each potential difference to generate in the grounding conductor and the power source conductor is made smaller to the utmost and the logical vibrational amplitude of each cell is smaller and the operating margin thereof is smaller, by a method wherein the power source conductor and the grounding conductor, which are respectively connected to each of the fundamental cells, are disposed in such a way as to orthogonally intersect. CONSTITUTION:A direct-coupled FET logic (DCFL) makes a fundamental cell 21 consist of one piece of DFETQ1 and three pieces of EFETs Q2-Q4 and the cell 21 is made to operate as a three-input NOR gate by properly performing a wiring as a whole. A power source conductor 22 is provided in such a way as to run in parallel with the columns and the grounding conductor is provided in such a way as to run toward the orthogonal direction to the columns. By making each fundamental cell in such a constitution, all the fundamental cells can be stably operated even though the cells are respectively composed of the DCFL constitution, wherein each potential difference to generate in the grounding conductor and the power source conductor is made smaller to the utmost and the logical vibrational amplitude of each cell is smaller and the operating margin thereof is smaller.

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Inventors:
IGAWA YASUO
TOYODA NOBUYUKI
KANAZAWA KATSUE
MIZOGUCHI TAKAMA
HOUJIYOU AKIMICHI
Application Number:
JP796484A
Publication Date:
August 10, 1985
Filing Date:
January 20, 1984
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H01L27/095; G11C5/02; G11C5/06; G11C5/14; H01L21/82; H01L21/822; H01L27/04; H01L27/118; (IPC1-7): H01L27/04; H01L29/80
Other References:
J.J.OF APPLIED PHYSICS=1983
Attorney, Agent or Firm:
Takehiko Suzue



 
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