PURPOSE: To shorten an access time, by connecting an emitter follower using a PNP transistor together with another emitter follower using an NPN transistor to a word line and complementarily driving these transistors.

CONSTITUTION: When levels of input signals Vin1 and Vin2 are changed and the electric potentials of the base of transistors (Tr) Q1 and Q2 are lowered, the electric potential of the base of an NPN Tr Q3 is made higher than that of a word line W and a large collector current is made to flow to the Tr Q3 and, at the same time, a PNP Tr Q4 is cut off by the electric potential of a node N2. Therefore, an electric current is made to flow through the line W and the stray capacity Cs of the line W and equivalent capacity of a memory cell are charged and the level of the line W rises rapidly. When one side of the input signals is changed into a high signal, electric charges of stray capacity Cs, etc., are attracted by a constant-current source 1b and the electric potential of the word line W is slowly lowered. Since the falling speed of the electric potential of the node N2 is much faster than that of the line W, the Tr Q4 is strongly turned on and a large collector current is made to flow and the electric potential of the word line W rises rapidly, when the electric potential of the base of the Tr Q4 is further lowered by the amount of VBE from the electric potential of the line W.