PURPOSE: To increase remarkably the converting speed, by dividing a resolution step into two stages, determining bits of a half bits of the highorder in n/2-bit of the resolution and determining bits of a half the bits of the low-order in n-bit of the resolution.

CONSTITUTION: Resistors connected in series comprising resistors Rn(N=1∼8) with binary weighting are impressed with reference voltages, +VREF and -VREF, and a voltage corresponding to each resistor Rn is charged in a capacitor Cn (n=1∼8) whose one end is grounded. The C1∼Cn are connected in series by operating switches S1∼S4 to compare the voltage at series connection of the capacitors with an analog input, and high-order bits are decided at down-counters DC1∼DC4 from the result of comparison in n/2-bit of the resolution. After the C1∼C8 are charged, all the capacitors are connected in series with the switches S1∼S7, the voltage is compared 1 with the analog input and the low- order bits are decided at up-counters UC1∼UC4 from the result of comparison in n-bit of the resolution.