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Patent Searching and Data


Title:
MANUFACTURE OF SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS5856452
Kind Code:
A
Abstract:

PURPOSE: To enable to form other electrodes by self-aligning at a pair of electrodes of an MOS capacity without necessity of masking by forming a resist film as a spacer of a lift-off method as it is and forming the other electrode.

CONSTITUTION: An isolation region 22 and a gate oxidized film 23 are formed, the prescribed pattern resist film 14 is then formed, with the film 24 as a mask implanting n type impurity ions, and an ion implantation layer 25 to become one electrode of an MOS capacity is formed. Then, while the film 24 is allowed to remain, a conductive layer made of high melting point metal or its silicide is accumulated by a sputtering method. At this time, the conductive layer is isolated into the conductive layer 26a on the film 23 and the conductive layer 26b on the film 24. When the film 24 is removed in this state, the layer 26b is also removed together, only the layer 26a remains. The layer 26a forms the other electrode of the MOS capacitor.


Inventors:
TANAKA TAKESHI
Application Number:
JP15513481A
Publication Date:
April 04, 1983
Filing Date:
September 30, 1981
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L27/10; H01L21/8242; H01L27/108; (IPC1-7): G11C11/34; H01L27/10; H01L29/86
Attorney, Agent or Firm:
Takehiko Suzue