PURPOSE: To attain the arithmetic processing at a high speed by obtaining an optional logical block in a module structure and multiplexing this module to apply the parallel arithmetic processing.

CONSTITUTION: The input and output registers of arithmetic modules M0WM3 are connected in parallel to the output data 15 which is delivered to a data receiving part 18 as well as the input data 12 given from a data supply part 17 respectively. The control latches 5 and 6 of each arithmetic module are connected in series to each other. Furthermore, the 1st trigger signal 11 of the module M3 is connected as the 1st trigger signal of the module M0. The signal 11 is produced in a cycle 4τ and applied to the latch 5 of the module M0. As a result, the signal 11 is converted into the 1st enable signal delayed by 1τ to turn the input register into an enable state and then connected as the 1st trigger signal of the module M1. In such a way, the input registers of the arithmetic modules are scanned successively and turned into an enable state respectively.