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Title:
DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPH04127711
Kind Code:
A
Abstract:

PURPOSE: To reduce energy consumption by parallelly arranging plural delay elements so as not to operate them simultaneously.

CONSTITUTION: An input changeover switch 6 is changed over to apply input signals to delay elements (shift registers) 41-4i to which a frequency divider 5 applies the significant part of a shift clock. The input signals are successively supplied to the respective shift registers 41-4i synchronously with the input clock, and the shift registers 41-4i supplied the input signals shift internal data. An output changeover switch 7 is changed over to apply the outputs of the shift registers 41-4i to a data output terminal 3 in the order of executing shift operation. Thus, since the respective shift registers 41-4i are operated by the shift clock outputted from the frequency divider 5 so as to execute time division operations, the energy consumption can be reduced.


Inventors:
KUME ATSUYA
Application Number:
JP24938990A
Publication Date:
April 28, 1992
Filing Date:
September 19, 1990
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K5/135; (IPC1-7): H03K5/135
Attorney, Agent or Firm:
Hiroaki Tazawa (2 outside)



 
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