PURPOSE: To compare a predicate with a predicate in parallel by allowing plural coincidence detectors to check the coincidence between two predicates read out of plural buffer memories.

CONSTITUTION: When an address specified by an address register 101 is sent to a storage device 100, the output is stored in one of buffer memories 102, 104, 106, and 108. The output of the buffer memory is sent to a selecting circuit 110, 111, 114, or 115 through a data line 203, 204, 205, or 206. The selecting circuits 110 and 111, and 114 and 115 select and input one output among data lines 203W206 and a data line 218 which outputs data from a control part 113 to comparators 112 and 116, so that coincidence signals as comparison outputs are sent to the control part 113. The control part 113 inputs the coincidence signals and operates the stack register and register in the control part 113.