Title:
MASTER SLICE LSI SUBSTRATE
Document Type and Number:
Japanese Patent JPS59117132
Kind Code:
A
Abstract:
PURPOSE:To prevent local wiring contact by arranging the memory region in contact with the upper side of internal wiring region with the same width as the cell array. CONSTITUTION:An input/output buffer circuit 21, an input/output buffer circuit having an input pad 22, a cell array 9, an internal wiring region having wiring region 8, a memory region 7, a temporary external terminal 23, an RAM terminal 71, a buried layer 24 connecting the circuit 21 and terminal 23 and a leadout wire 232 connecting the circuit 21 and the temporary external terminal 231 are formed on an LSI substrate 1. Since the region 7 is arranged in contact with the upper side of the internal wiring region 3 in the same width as the cell array 9, it is no longer necessary to wire bridging over the region 7 and the detour of wiring is not required.
Inventors:
NOMURA MINORU
Application Number:
JP23241782A
Publication Date:
July 06, 1984
Filing Date:
December 23, 1982
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/822; H01L21/82; H01L27/04; H01L27/118; (IPC1-7): H01L27/04
Attorney, Agent or Firm:
Uchihara Shin