Title:
METHOD FOR MONITORING TEST OF PLANAR TYPE SILICON SEMICONDUCTOR SUBSTRATE
Document Type and Number:
Japanese Patent JPS59115535
Kind Code:
A
Abstract:
PURPOSE:To determine a defective or non-defective dicision on the lot of the substrate to which a sampled substrate belongs by a method wherein a plurality of planar type Si substrates on which a plurality of planar type elements are arranged are prepared at the same time, and when at least any one piece of them is picked out for sampling, the sampled piece is subjected to the soldering condition examination in advance. CONSTITUTION:The P-N junction formed on the surface layer of an Si substrate 1 is covered by an oxide film 2, an electrode part and a part of the oxide film 2 are covered by a metal film 3, and a planar substrate is formed. The above substrate is manufactured in a large lot simultaneously, and at least one of them is picked out and an examination is performed on it. The substrate 1 picked out for the examination is placed on a conveyor belt 7 through the intermediary of a heat-resisting carbon jig 4, and the above is passed through an oven 6 of hydrogen atmosphere which is heated up to the solder fusing temperature or above by a heater 5 located on the outer circumference. Subsequently, a defective or non-defective decision is determined to the substrate 1 when it came out to outside of the oven 6 using a prober, and when a decision is determined in such a manner that there are too many defective substrate and the yield rate is low, all substrates in the same lot of manufacture is considered as defective.
Inventors:
TSUDA SHIGERU
Application Number:
JP22568982A
Publication Date:
July 04, 1984
Filing Date:
December 22, 1982
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD
International Classes:
H01L21/66; (IPC1-7): H01L21/66
Attorney, Agent or Firm:
Iwao Yamaguchi