PURPOSE: To write data easily to a memory which needs a long data fixing period from a CPU having a short data fixing period, by writing the write data given from the CPU to a memory after holding it temporarily.

CONSTITUTION: Signal holding circuits 7 and 8 are set before the write data input and the address input of a memory 1. For the address input, a switching circuit 9 is provided to supply the held signal in a write mode and the direct address signal in a read mode respectively. In the read mode an address signal is sent to the memory 1 within an access period of a CPU3 and the data is readout. While both the data and address signal given from the CPU3 are held temporarily and the data is written to the memory 1 between an access period and the next access period in the write mode. In such a way, the data can be written easily to the memory 1 requiring a long data fixing period from a CPU having a short data fixing period.