PURPOSE: To suppress the issue of a counter station alarm even if a counter station alarm bit is detected erroneously by setting an error detecting circuit to a state that an error is present thereon when frame synchronizing step-out occurs.

CONSTITUTION: When a code error by a transmission line 1 rises and a frame detecting circuit 2 is in the frame synchronizing step-out, an error detecting circuit 3 is set to a state that an error is present thereon by the output signal '1' of a frame detecting circuit 2, and outputs a signal '0'. An AND circuit 6a takes the AND gate of an output of the frame pattern detecting circuit 2 and the output of the error detecting circuit 3, and an AND circuit 6b takes the AND gate of an output of the AND circuit 6a and the output of a counter station alarm detecting circuit 4. Subsequently, the outputs of the frame pattern detecting circuit 2, the AND circuit 6a and the AND circuit 6b are generated as the alarm signals of this frame synchronization detecting circuit in this receiving terminal station.