PURPOSE: To decrease the current consumption of a data line by dividing the memory and cell and block configuration of a word unit through a logic gate into plural pieces connecting said pieces with a common data line and separately reading out said blocks by selection of an X decoder.
CONSTITUTION: Word lines WL.L and WL.R of memory are devided to the right/left through an X decoder for every 16 rows of one-block 32-row memory cells so as to simultaneously input/output eight bits of memory cell MC selection. By taking logic with one address signal, for example, A8 in the X decoder XDEC, either of left word line WL.L or right word line WL.R is activated. As a result, the word lines for memory cell selection is reduced to half, and the current consumption flowing through a data line load MOS transistor LMOS, and the memory cell MC can be reduced to half.
MINATO OSAMU
SASAKI YUKIO
KINOSHITA MASAMI
MASUHARA TOSHIAKI
| JPS51163830U | 1976-12-27 | |||
| JPS5619584A | 1981-02-24 | |||
| JPS5668988A | 1981-06-09 | |||
| JPS5694576A | 1981-07-31 |