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Title:
METHOD FOR READING OUT OF MEMORY CIRCUIT
Document Type and Number:
Japanese Patent JPS60150291
Kind Code:
A
Abstract:

PURPOSE: To perform a high speed read out with a small chip area by simultaneously supplying information read out from plural digit lines to plural common data lines respectively, and reading out the information from a selected data line out of the plural common data lines.

CONSTITUTION: Information of digit lines D1 and D2 is transferred to data bus lines RB2 and RB1 respectively. The lines RB1 and RB2 are inputted to a data selector circuit 5. The data selector circuit 15 transfers the information of only one of the data bus lines selected by a Y-decoder (2) 14 to a terminal READ OUT through an amplifier 21. The method inputs the write first in the circuit 15 given to the terminal WRITE IN through an amplifier 21, selects the data bus line to be written by the Y-decoder (2) 14, transferred the write in data to the data bus line the write in data of which are selected, connects the write in to the data bus line to transmit the write in only to one of the digit lines to be selected by the Y-decoder (1) 4.


Inventors:
TOKUSHIGE KAZUO
Application Number:
JP24853884A
Publication Date:
August 07, 1985
Filing Date:
November 22, 1984
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C11/41; G11C7/00; G11C11/34; (IPC1-7): G11C7/00
Attorney, Agent or Firm:
Uchihara Shin



 
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