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Title:
ABNORMALITY DETECTOR
Document Type and Number:
Japanese Patent JPS605344
Kind Code:
A
Abstract:

PURPOSE: To speed up the recovery to normal operation by detecting edges of an output signal of a specific period to be processed in time series, and resetting a processor when the level of the signal generated by integrating the edges is larger than a set value.

CONSTITUTION: The output signal of a microcomputer 1 is supplied to an edge detecting circuit 4 to detect edges. Its edge detection output is integrated by an integrating circuit 8 to detect whether the integral output is within a specific level range set by a 2-level detecting circuit 10 or not. When the output is not within the specific level range, a flip-flop 13 is triggered and the microcomputer 1 is reset through a resetting circuit 3. Consequently, the recovery from abnormal operation to normal operation is performed speedily.


Inventors:
HATA TOSHIAKI
Application Number:
JP11482583A
Publication Date:
January 11, 1985
Filing Date:
June 23, 1983
Export Citation:
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Assignee:
SOGO JIDOSHA ANZEN KIKAI
International Classes:
G06F11/30; G06F11/00; (IPC1-7): G06F11/00
Attorney, Agent or Firm:
Masuo Oiwa



 
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