PURPOSE: To absorb both forward and backward surge pulses by forming an n+ type buried layer as a protection resistance and allowing an input pulse to escape through utilization of the forward and backward npn transistor comprising an n- type semiconductor region, p type diffused region and n+ type diffused region.
CONSTITUTION: When a forward surge pulse enters the electrode in the side of input terminal B, a voltage drops due to a resistance R while a surge current I0 flows in the n+ type buried layer 5. Thereby, a forward npn transistor Q1 (composed of the n- type semiconductor region 6a, p type semiconductor region 9 and n+ type semiconductor 10) operates and a current I1 flows into the ground electrode passing through the electrode on n+ type diffused region 10. When a backward surge pulse enters, a negative surge current flows to the side of circuit A through the n+ type buried layer 5, resulting in voltage drop. Therefore, a backward npn transistor Q2 where the p type region 9 is formed as the base, the n+ type diffused region 10 as the collector and n- type semicondutor region as the emitter operates and a current I2 flows to the side of input terminal B.
TAKIGAWA AKIRA
IHARA HIROSHI
IWASAKI ISAO
WATABE TOMOYUKI
HITACHI MICROCUMPUTER ENG
AKITA DENSHI KK
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