PURPOSE: To obtain a signal processor which performs interlacing easily and has the small possibility of smear generation by driving specific one of horizontal shift registers and distributing its output to plural vertical shift registers.

CONSTITUTION: Each horizontal shift register 4 is so constituted as to perform photoelectric conversion by itself and, for example, 525 registers are arranged corresponding to one frame of a TV screen. Further, vertical shift registers 5 have bits at least as many as the horizontal shift registers 4. When a pulse 1 is inputted to a shift register 8, outputs A∼D of the shift register 8 are switched to a high-level signal in order and passed through AND gates 7 to drive horizontal shift registers 4. At this time, odd-numbered lines of the horizontal shift registers are read out in sequence firstly and even-numbered lines are read successively to output one-frame information as a two-field signal, so that a leak of the signal and crosstalk are reduced.