DATA PROCESSOR

Japanese Patent JPS589277

A

The replacement selection of entries in a second level (L2) cache directory of a storage hierarchy is controlled using replaced and hit addresses of a dynamic look-aside translation buffer (DLAT) at the first level (L1) in the hierarchy which receives CPU storage requests along with the CPU cache and its directory. The DLAT entries address page size blocks in main storage (MS). The disclosure provides a replacement (R) flag for each entry in the L2 directory, which represents a page size block in the L2 cache. An R bit is selected and turned on by the address of a DLAT replaced page which is caused by a DLAT miss to indicate its associated page is a candidate for replacement in the L2 cache. However, the page may continue to be accessed in the L2 cache until it is actually replaced. An R bit is selected and turned off by a CPU request address causing a DLAT hit and a L1 cache miss to indicate its associated L2 page is not a candidate for replacement. When a small proportion of CPU requests bypass of the DLAT (e.g. real address requests), a L1 request address having a L1 cache miss may be used to turn off the R bit, and any replaced line address may be used to turn on the R bit, for the L2 entry selected by that address. L2 LRU replacement selection circuits generate a LRU pointer to another entry in the congruence class of the selected entry when its R flag is change from a no replacement state to a replacement state. Each turn off signal to an R flag may generate a new LRU pointer for its congruence class which also points away from the selected entry.

ROBAATO PAASHII FURETSUCHIYAA

JP11261682A

January 19, 1983

July 01, 1982

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IBM

G06F12/08; G06F12/10; G06F12/12; (IPC1-7): G06F13/00; G11C9/06

Koichi Tonmiya

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