Title:
PAM TYPE INVERTER DEVICE
Document Type and Number:
Japanese Patent JPS59175382
Kind Code:
A
Abstract:
PURPOSE:To reduce the size of a PAM type inverter device and to improve the reliability by memorizing the variation of a voltage control pattern in a memory circuit, thereby reducing the memory capacity of the memory circuit. CONSTITUTION:A switching element 6 is inserted to a positive potential line between a DC converter 1 and an inverter 3, and the duty ratio of the conduction and nonconduction is varied by a control signal from a controller 5'. The variation in the output voltage corresponding to the variation in the voltage control pattern, i.e., the output frequency is memorized at every pattern in a memory circuit 53' in the controller 5', the output voltage data from the memory circuit 53' is read out corresponding to the output frequency by a CPU 54', and the output voltage is controlled by altering the conducting timing of the switching element 6 by the control signal from the voltage controller 56' by the value.
Inventors:
KATSURAYAMA NORIYUKI
Application Number:
JP4813183A
Publication Date:
October 04, 1984
Filing Date:
March 23, 1983
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
H02M7/48; (IPC1-7): H02P13/20
Attorney, Agent or Firm:
Takehiko Suzue