Title:
LEVELLING SURFACE OF SEMICONDUCTOR SUBSTRATE
Document Type and Number:
Japanese Patent JPS5911632
Kind Code:
A
Abstract:
PURPOSE:To enable to level the surface of a semiconductor substrate by including at least steps of mask forming, annealing and etching. CONSTITUTION:A collector buried layer 8 is provided on the surface of an Si substrate 7, and an Si epitaxial layer 9 is formed thereon, by thermal oxidation of the surface of which is formed an SiO2 film 10 and further thereon an Si3N4 film 11 is formed. Deep grooves 121 and 122 of 2-4mum depth going through the collector buried layer 8 and reaching the substrate 7 are formed by etching Si. An SiO2 film 13 is formed by oxidization of the surface of the grooves 121 and 122 after annealing. At the final stage of etching where phosphorous ion is implanted to the outer layer 151 of SiO2 film 15 through Si3N4 film 16, the surface of the substrate 7 is levelled completely without protrusion 6. Insulation and separation among elements are completed by etching a photo-resist pattern 17, the exposed Si3N4 16 and Si3N4 14, and by etching lightly the surface of SiO2 15 to remove impurity introducing part in case of necessity.
Inventors:
KAWAJI MIKINORI
UCHIDA AKIHISA
TAKAKURA TOSHIHIKO
UCHIDA AKIHISA
TAKAKURA TOSHIHIKO
Application Number:
JP11978382A
Publication Date:
January 21, 1984
Filing Date:
July 12, 1982
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L21/306; (IPC1-7): H01L21/306
Attorney, Agent or Firm:
Toshiyuki Usuda
Previous Patent: A program, a control method of a game, and an information processor
Next Patent: PRODUCTION OF ALUMINUM PHOSPHATE SILICATE GLASS
Next Patent: PRODUCTION OF ALUMINUM PHOSPHATE SILICATE GLASS