PURPOSE: To obtain a semiconductor circuit having a high-speed operation with small power consumption and high density of integration, by connecting an enhancement type FET which receives application of clock at its gate in series to an enhancement-depletion type inverter.

CONSTITUTION: A clock pulse 1 is applied to a gate electrode 17 of an enhancement type IGFETQ6. The FETQ6 conducts when the pulse 1 is negative. Therefore, an outut signal is extracted from a drain 19 of an FETQ7 when a signal is supplied to a terminal 20. When the pulse 1 is zero, the FETQ6 becomes nonconductive. Thus no current flows to the semiconductor circuit to ensure small power consumption. At the same time, it is possible to keep a high- speed performance of an enhancement-depletion type inverter circuit.