PURPOSE: To reduce a circuit scale and to recognize many kinds of control information signals, by using a pattern in all combinations of assumed errors in many kinds of control information transmitted as addresses of a memory and outputting a control status signal from the memory.

CONSTITUTION: An input data 1 is given to a shift register 3 via an AND circuit 2, converted into a parallel data and applied to an address of an ROM4. The address is a pattern of all combinations of assumed errors of many kinds of transmitted control information, an the control status signal is used as the output of the ROM4 and fed to the control system of a cipher machine corresponding to the address. When the control status signal is detected, the AND circuit 2 is interrupted via an OR circuit 5, an FF6 and an inverter 7 to interrupt the data input. Further, when the input is interrupted externally, a stop pulse 9 is applied.