PURPOSE: To obtain a data processor with a simple constitution operated by a cache memory by providing a request control means and a switching control means to form a sub-model of a high speed data processor adopting two cache memories.

CONSTITUTION: An instruction word is stored in an instruction register 1 of a data processor to designate one entry of an index register 2. An output of the register 2, address shift and the base address of a base register 3 are added by an operand address adder 5 to produce a virtual operand address. A relative address of an instruction counter 4 and a base address are added by an instruction address adder 6 to produce a virtual address. The virtual operand address and the virtual address are fed to the cache memories 11, 16 via address switching circuit 7, 12 and address conversion buffers 9, 14 or the like. Then a high speed data processor adopting the 2 cache memories is formed as a sub-model to simplify the constitution of the data processor.