Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS59186332
Kind Code:
A
Abstract:
PURPOSE:To suppress the thermal strain generated by the operation of a transistor and avoid the thermal fatigue of a solder layer by a method wherein, when a transistor substrate is fixed to a supporting member made of a copper plate by a solder layer composed of lead-tin-silver, a loop shape metal member, whose thermal expansion coefficient is larger than that of Si and smaller than that of copper, is buried in the solder layer. CONSTITUTION:A transistor substrate 2 is conductively adhered on a supporting member 1 made of a copper plate by a solder layer 3 of 93.5% lead-5% tin- 1.5% silver system. At that time, a loop shape metal member 4, which has the intermediate thermal expansion coefficient between the thermal expansion coefficient of copper and the thermal expansion coefficient of Si, is buried in the solder layer 3. This member is composed of a compound metal plate which has a cut-out part 44 at its center. The compound metal plate is composed in such a way that an iron-36% Ni alloy layer 42 is sandwiched between copper layers 41 and 43 and these three layers are made solid by cold rolling. With this constitution, heat-cycle resistance of the solder layer 3 is improved.
Inventors:
KURIHARA YASUTOSHI
MINAGAWA TADASHI
YATSUNO KOUMEI
WAKUI TAKAYUKI
OOGAMI MICHIO
MINAGAWA TADASHI
YATSUNO KOUMEI
WAKUI TAKAYUKI
OOGAMI MICHIO
Application Number:
JP5930383A
Publication Date:
October 23, 1984
Filing Date:
April 06, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L21/52; H01L21/58; (IPC1-7): H01L21/58
Domestic Patent References:
| JP54146169B |
Attorney, Agent or Firm:
Katsuo Ogawa