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Patent Searching and Data


Title:
ELECTRONIC SWITCH CIRCUIT
Document Type and Number:
Japanese Patent JPS5912622
Kind Code:
A
Abstract:

PURPOSE: To decrease the transmission loss and to improve the attenuation, by combining an FET and a transistor(TR) being poled oppositely for suppressing the leakage of signal.

CONSTITUTION: A p-channel FET11p is connected in series between an input terminal A and an output terminal B and a collector and an emitter of an npn TR13n are connected respectively between the output terminal B and ground. Further, the gate of the FET11p and the base of the TR13n are connected together and the connecting point is taken as a control terminal C. Then, an output load Rout is connected between the output terminal B and ground. Further, when the FET is turned on, an input signal is transmitted to the output terminal via the FET and when the FET is turned off, the load is short-circuited resulting in suppressing the leakage of signal. The transmission loss is reduced in this way and the attenuation is improved by suppressing the leakage of signal. Moreover, when an n-channel FET is employed, a pnp TR is to be used.


Inventors:
OOTSUKA KOUZOU
Application Number:
JP12173782A
Publication Date:
January 23, 1984
Filing Date:
July 13, 1982
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H03K17/687; H03K17/567; (IPC1-7): H03K17/687
Attorney, Agent or Firm:
Takehiko Suzue