PURPOSE: To guarantee continuity of operation, by reading out a read-out data in accordance with clock driving, and setting it to a register, in case when a CPU stops a clock and accesses a memory by stepping the clock.

CONSTITUTION: A clock stop of a CPU side is informed to a main storage device MMU side through a CLOCK-STEP signal. As for the device MMU, the clock does not stop even if the CPU side clock stops. Accordingly, Data which are read out from memory modules 57, 58 are sent to a read-out data bank switching circuit 60 through buses 208, 209, and the memory module is selected. The data whose module is selected is sent to a read-out and write data bank switching circuit 61. Therefore, the data of a bus 210 is transferred to a bus 211, and is inputted to data registers 62, 64. As for the data which are set to the register, one is sent to the CPU through a bus 214, and the other is sent to a write data and a rewrite data switching circuit 53, by which clock stepping is executed by the CPU side.