Title:
MULTIPLIER
Document Type and Number:
Japanese Patent JPS59114634
Kind Code:
A
Abstract:
A complement carry technique and a staged skipping technique are employed for multipliers using four or more stages of carry save adders (A1....A7), to allow slower bits (S41) to skip past a stage while faster bits (C40) must go through that stage, thereby speeding up the multiplier's overall speed of operation. The complement carry technique minimizes hardware by allowing sums and carries to be generated by the carry save adders (A1....A7) in either a true or a complement form. The skip technique takes advantage of the fact that the generation of a carry bit is faster than the generation of a sum bit. In the case of a four stage carry save adder designed for a multiplier, the skip technique reduces the number of circuit delays from the existing eight to the improved seven, without the addition of any hardware. Thus, the technique can result in a speed improvement for a multiplier.
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Inventors:
BURAIAN REIMONDO MAASHII
Application Number:
JP18086583A
Publication Date:
July 02, 1984
Filing Date:
September 30, 1983
Export Citation:
Assignee:
IBM
International Classes:
G06F7/50; G06F7/508; G06F7/53; G06F7/509; G06F7/52; G06F7/527; (IPC1-7): G06F7/52
Domestic Patent References:
| JPS4886448A | 1973-11-15 | |||
| JPS5541600A | 1980-03-24 |
Attorney, Agent or Firm:
Koichi Tonmiya