PURPOSE: To enable to accomplish high integration of the titled semiconductor device by a method wherein the contact holes are formed in a source and drain region by performing a self-alignment.

CONSTITUTION: A thin insulating layer 22 and a field insulating layer 23 are formed on a one-conductive type Si semiconductor substrate 21. Then, a polycrystalline Si layer 25 and an insulating layer 26 are successively formed on the whole surface, and a photoresist layer 27 is coated on the part corresponding to the gate part located on the surface of the layer 26. Then, the layers 25 and 26 are selectively removed by performing an etching using the layer 27 as a mask, and a gate part is formed. Subsequently, a source region 28 and a drain region are formed using said gate part as a mask. Then, an insulating layer 30 is grown on the whole surface. Then, a directional etching is performed on the layer 30 in such a manner that the surface of the regions 28 and 29 will be exposed and that the layer 30 will be left on the side part of the electrode 25. Then, Pt is vapor-deposited on the whole surface, a heat treatment is performed, and the regions 28 and 29 are formed into platinum silicide. Then, after Pt 32 has been removed, a source electrode 33 and a drain electrode 34 are formed.