Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
BUFFER MANAGEMENT SYSTEM OF DIRECT MEMORY ACCESS
Document Type and Number:
Japanese Patent JPS60168257
Kind Code:
A
Abstract:

PURPOSE: To perform the reception processing in a high speed by taking out the start address and the size of data to the DMA (direct memory access) -transferred and setting them into a DMA transfer circuit before DMA transfer.

CONSTITUTION: Before reception, a CPU2 sets the start address of a memory 3, to which data should be DMA-transferred, and the size of transfer data to a first in first out circuit 6 by address and data size storage signals. Next, the CPU2 issues a DMA transfer indication to a DMA transfer circuit 4, and the circuit 4 issues a read signal for the purpose of reading the start address and the transfer data size. When the address and the data size are read as responses of the read signal, they are set to the circuit 4, and data transfer from a data circuit 5 to the memory 3 is started.


Inventors:
KAWAI ATSUO
TOKI RIYUUICHI
ISHII MINORU
YASHIRO ZENICHI
NISHIWAKI MINEO
Application Number:
JP2180884A
Publication Date:
August 31, 1985
Filing Date:
February 10, 1984
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTD
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F13/28; (IPC1-7): G06F13/38
Attorney, Agent or Firm:
Akio Takahashi