Title:
JOSEPHSON INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS60110182
Kind Code:
A
Abstract:
PURPOSE:To suppress the presence of a microleakage in the interior by forming at least an insulating layer between a ground plane and a lower electrode in a multilayer structure of a silicon oxide film and a silicon dioxide film. CONSTITUTION:Lower and upper electrodes 3, 4 made of superconductive material such as a lead alloy, and insulating layers 5a, 6a, 7 are laminated on a ground plane 2 made of superconductive material such as niobium and coated on a silicon substrate 1 to form a Josephson junction 8. The layers 5a, 6a are superposed with silicon monoxide films 52, 62 on insulating films 51, 61, and even if pinholes are generated in the films 52, 62, the presence of microleakage can be suppressed to prevent the deterioration of the characteristics.
Inventors:
OBARA SHIROU
Application Number:
JP21741783A
Publication Date:
June 15, 1985
Filing Date:
November 18, 1983
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L39/22; (IPC1-7): H01L39/22
Attorney, Agent or Firm:
Sadaichi Igita