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Title:
ADDRESS ASSIGNMENT SYSTEM
Document Type and Number:
Japanese Patent JPS5916059
Kind Code:
A
Abstract:

PURPOSE: To improve considerably the degree of freedom for the allocation of a memory area at designing a system, by providing a comparator which detects the coincidence between the contents of the base address register of a program stroage part and the contents of the high-order part of a program counter.

CONSTITUTION: The base address register 3 and the high-order address part 21 of the program counter 2 have the same number of bits, and their contents are sent to and compared by the comparator 4 with each other. Consequently, when they coincide with each other, a coincidence signal 13 is made active and codes out of an ROM1 are outputted to an internal bus 12 through an ROM output buffer 7. When they do not coincide, a data buffer 8 is activated through the operation of an inverter 11 and codes stored in an external memory are fetched to the bus 12. At this time, the buffer is place in a high-impedance state to inhibit transfer from the ROM1 to the code bus 12.


Inventors:
TANABE TERUMASA
Application Number:
JP12388582A
Publication Date:
January 27, 1984
Filing Date:
July 16, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F12/06; G06F9/26; G06F9/445; (IPC1-7): G06F9/30; G06F13/00
Domestic Patent References:
JPS5740790A1982-03-06
Attorney, Agent or Firm:
Uchihara Shin