Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS59161838
Kind Code:
A
Abstract:
PURPOSE:To prevent the generation of N-P junction leakage current to occur at the side surfaces of an isolating region by a method wherein when the buried element isolating region is provided in a semiconductor device, a P type inversion preventing layer is provided on the undersurface of an N type diffusion layer to come in contact to the region. CONSTITUTION:A groove is bored in the surface layer on a P type Si substrate 1 and in the groove is buried a separating material 12 for using the groove as an element isolating region 13. Interposing the region 13 between, an N channel MOS transistor is formed on one side and a P channel MOS transistor is formed on the other side. Namely, on the N channel element side are formed by diffusion a source region 171 and a drain region 181, both of which are a shallow N<+> type one, and a gate electrode 161 is attached to these regions through a gate insulating film 151 formed between the regions 171 and 181. In this constitution, a P<-> type conversion preventing region 10 is provided under the undersurface of the region 181, which comes in contact to the region 13. Though the resion 171 side is not illustrated in the diagram, a conversion preventing region is formed on the region side as well. On the other hand, on the P channel element side is formed an N type well region 14, and a source region 172 and a drain region 182, both of which are a P<+> type one, are provided here as well. However, the inversion preventing region becomes unnecessary here by specifying the concentration of the well region 14.
Inventors:
NAGAKUBO YOSHIHIDE
Application Number:
JP3692083A
Publication Date:
September 12, 1984
Filing Date:
March 07, 1983
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
H01L27/08; H01L21/76; H01L21/762; (IPC1-7): H01L27/08; H01L29/78
Domestic Patent References:
| JPS5578541A | 1980-06-13 |
Attorney, Agent or Firm:
Takehiko Suzue