BASIC CELL FOR GATE ARRAY OF INTEGRATED CIRCUIT - CSELT CENTRO STUDI LAB TELECOM

Title:

BASIC CELL FOR GATE ARRAY OF INTEGRATED CIRCUIT

Document Type and Number:

Japanese Patent JPS59938

Kind Code:

A

Abstract:

A basic cell for integrated-circuit gate arrays comprises four transistors (T1, T2, T3, T4), two of which (T2, T3), symmetrical with respect to a cell central point, have the gate electrode (C, C'), connected by a polysilicon pass (1) traversing the metal power lines (Vss, Vdd). A second polysilicon pass (2) connects opposite areas with respect to a zone defined by the metal power lines. The contacts (A, B, C, C', D, D', E, E', G, G', H, H', I, I') associated with the transistor electrodes are arranged so as to minimize the cell surface.

Inventors:

MARUKO GANDEIINI
DANTE TOREBUISAN

Application Number:

JP5880883A

Publication Date:

January 06, 1984

Filing Date:

April 05, 1983

Export Citation:

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Assignee:

CSELT CENTRO STUDI LAB TELECOM

International Classes:

H01L21/82; H01L27/02; H01L21/8238; H01L27/092; H01L27/118; (IPC1-7): H01L21/82; H01L27/08

Attorney, Agent or Firm:

Kazuho Kawarada

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