ISOLATING METHOD FOR ELEMENT OF SEMICONDUCTOR DEVICE

Japanese Patent JPS5957450

A

PURPOSE:To obtain the method, through which a semiconductor single crystal layer can be insulated from a fine pattern of 1mum or more in the depth of 1mum or more and size can be controlled easily, by providing a forming process for the pattern of a first insulator layer, a forming process for a second insulator layer, a process removing one part of the first insulator layer and a process depositing the semiconductor single crystalline layer. CONSTITUTION:The first insulator layer 32 is formed to the surface of a P type silicon substrate 31 in approximately 1mum thickness, and etched selectively until the surface of the silicon substrate 31 is exposed, and the first insulator layer 32 is shaped so that vertical side walls are formed. The second insulator layer 33 is formed in approximately 0.2mum thickness, and the second insulator layer 33 except sections depositing on the side walls of the first insulator layer 32 is removed through etching. A field region except a region in which the semiconductor single crystal layer must be formed is coated with a resist 34, the first insulator layer 32 is removed through a normal etching method, the resist 34 is removed, and the semiconductor single crystal layer 35 is grown between the second insulator layers 33.

JPS62206874	SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
JP2024022428	semiconductor equipment
JPH03148852	SEMICONDUCTOR DEVICE

ENDOU NOBUHIRO

JP16781682A

April 03, 1984

September 27, 1982

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NIPPON ELECTRIC CO

H01L21/76; H01L21/302; H01L21/3065; H01L21/78; (IPC1-7): H01L21/302

JPS498188A	1974-01-24
JPS57111032A	1982-07-10

Uchihara Shin

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